The present invention relates to a field-effect transistor and a method for manufacturing a field-effect transistor and in one embodiment to an ohmic source-poly contact for a poly-poly MOS switch.
Increasing integration densities of semiconductors have the consequence that a limitation of power losses gains an ever greater importance. Power losses may develop in different locations. In modern integrated circuits, switches are mainly realized by transistors and for a low-loss operation it is important that in an on state, the switch operates as loss-free as possible, which corresponds to a resistance value which is as low as possible. This means, that an input resistance Ron of the switch has to be kept as low as possible. Possible transistors which are suitable as switches are, for example, MOS power transistors which include a high switching speed. Thus, for longer phases of operation, for example, of more than one nanosecond, the input resistance Ron of the MOS power transistor may be substantially decreased. It is desirable anyway that the input resistance value Ron is as low as possible, but this means for example, that Ron again drops by some percents, if the transistor remains in a on state, for example, for longer than one nanosecond, and that thus the power loss again decreases.
This improvement of the on resistance Ron is, for example, dependent on the chip size, as only the portion of the input resistance Ron may be improved which is formed in the channel area of the power transistor. Further influential factors which influence the input resistance Ron are, for example, the chosen contacting of the power transistor. For a switch realized by a power transistor, thus, apart from an optimization of the terminal contacts, an optimization of the channel portion at the input resistance Ron is desirable.